module SeqGen(
  rst_n,
  clk,

  data_valid,
  seq_out
);

input wire rst_n;
input wire clk;

output reg data_valid;
output reg seq_out;


reg [7:0] Sequ;

always @ ( posedge clk )
begin 
 if(!rst_n ) begin 
  Sequ <= 8'b1101_0110;
 end
 else begin 
  Sequ <= {Sequ[6:0],Sequ[7]};//位拼接符号实现循环移位
 end 
end 
 
always @ ( posedge clk )
begin 
 if(!rst_n ) begin 
  seq_out <= 1'b0;
  //data_valid <= 1'b0;
 end
 else begin 
  seq_out <= Sequ[7];
  //data_valid <= 1'b1;
 end 
end

endmodule